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» A Network of Time-Division Multiplexed Wiring for FPGAs
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NOCS
2008
IEEE
13 years 11 months ago
A Network of Time-Division Multiplexed Wiring for FPGAs
Rosemary M. Francis, Simon W. Moore, Robert D. Mul...
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
13 years 10 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
FPL
2005
Springer
112views Hardware» more  FPL 2005»
13 years 10 months ago
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Anthony J. Yu, Guy G. Lemieux