497 search results - page 2 / 100 » A Network on Chip Architecture and Design Methodology |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...
LCN
2003
IEEE
13 years 10 months ago
2003
IEEE
The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, ev...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
DAC
2010
ACM
13 years 6 months ago
2010
ACM
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...