8 search results - page 1 / 2 » A New Approach for Computation of Timing Jitter in Phase Loc... |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with mod...
ICC
2007
IEEE
13 years 11 months ago
2007
IEEE
—The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the ...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time an...
SPIN
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. We present a new decision procedure for detecting property violations in pushdown models for concurrent programs that use lock-based synchronization, where each thread’...