465 search results - page 2 / 93 » A New Approach for Low Power Scan Testing |
DFT
1999
IEEE
13 years 9 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
DFT
2005
IEEE
13 years 7 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
DATE
2010
IEEE
13 years 7 months ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...