87 search results - page 4 / 18 » A New Approach to Test Generation and Test Compaction for Sc... |
ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
DATE
2008
IEEE
14 years 7 days ago
2008
IEEE
Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel...
VTS
2000
IEEE
13 years 10 months ago
2000
IEEE
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...