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DATE
1999
IEEE

Sequential Circuit Test Generation Using Decision Diagram Models

11 years 9 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning and conformity test generation procedures. Structural faults in both, datapath and control part are targeted. High-level simplified and fast symbolic path activation strategy is combined with random local test pattern generation for functional units. Current approach has achieved high fault coverages for known sequential circuit benchmarks in a very short time.
Jaan Raik, Raimund Ubar
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where DATE
Authors Jaan Raik, Raimund Ubar
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