29 search results - page 5 / 6 » A New Crosstalk Noise Model for DOMINO Logic Circuits |
ISQED
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract— To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, stagg...
ISPD
1999
ACM
13 years 10 months ago
1999
ACM
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Twisted differential line structure can effectively reduce crosstalk noise on global bus, which foresees a wide applicability. However, measured performance based on fabricated ci...