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TVLSI
1998
123views more  TVLSI 1998»
13 years 5 months ago
On-line fault detection for bus-based field programmable gate arrays
Abstract—We introduce a technique for on-line built-in selftesting (BIST) of bus-based field programmable gate arrays (FPGA’s). This system detects deviations from the intende...
N. R. Shnidman, William H. Mangione-Smith, Miodrag...
VTS
2003
IEEE
119views Hardware» more  VTS 2003»
13 years 10 months ago
A Circuit Level Fault Model for Resistive Opens and Bridges
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. ...
ETS
2007
IEEE
109views Hardware» more  ETS 2007»
13 years 11 months ago
Test Configurations for Diagnosing Faulty Links in NoC Switches
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
Jaan Raik, Raimund Ubar, Vineeth Govind
GLVLSI
1999
IEEE
92views VLSI» more  GLVLSI 1999»
13 years 9 months ago
Fault Coverage Estimation for Early Stage of VLSI Design
This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with ...
Von-Kyoung Kim, Tom Chen, Mick Tegethoff
MTDT
2000
IEEE
137views Hardware» more  MTDT 2000»
13 years 9 months ago
Diagnostic Testing of Embedded Memories Based on Output Tracing
A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a give...
Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Red...