11 search results - page 1 / 3 » A New Gate Delay Model for Simultaneous Switching and Its Ap... |
DAC
2001
ACM
14 years 5 months ago
2001
ACM
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...