18 search results - page 3 / 4 » A New Partitioning Method for Parallel Simulation of VLSI Ci... |
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order re...
VLSI
2007
Springer
13 years 12 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
GLVLSI
2009
IEEE
14 years 15 days ago
2009
IEEE
The miniaturization of transistors in recent technology nodes requires tremendous back-end tuning and optimizations, making bug fixing at later design stages more expensive. Ther...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
VLSID
2004
IEEE
14 years 6 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...