45 search results - page 8 / 9 » A New System Design Methodology for Wire Pipelined SoC |
CCECE
2006
IEEE
13 years 12 months ago
2006
IEEE
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
CAV
1999
Springer
13 years 10 months ago
1999
Springer
The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of In...
DATE
2009
IEEE
14 years 16 days ago
2009
IEEE
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
EMSOFT
2009
Springer
14 years 10 days ago
2009
Springer
System-on-Chip (SoC) is a promising paradigm to implement safety-critical embedded systems, but it poses significant challenges from a design and verification point of view. In ...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
Although processor design verification consumes ever-increasing resources, many design defects still slip into production silicon. In a few cases, such bugs have caused expensive...