24 search results - page 2 / 5 » A Novel Clocking Strategy for Dynamic Circuits |
APCCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
ISCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
A novel connection between digit-serialcomputationand skew-tolerant domino circuit design is exploited to create very efficient implementations of FIR digital filters. In our ap...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
Enabled by the continuous advancement in fabrication technology, present day synchronous microprocessors include more than 100 million transistors and have clock speeds well in ex...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...