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» A Novel Low Power Energy Recovery Full Adder Cell
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GLVLSI
1999
IEEE
91views VLSI» more  GLVLSI 1999»
13 years 9 months ago
A Novel Low Power Energy Recovery Full Adder Cell
A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder...
R. Shalem, Lizy Kurian John, Eugene John
ISLPED
1999
ACM
160views Hardware» more  ISLPED 1999»
13 years 9 months ago
Mixed-swing quadrail for low power dual-rail domino logic
This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full ad...
Bharath Ramasubramanian, Herman Schmit, L. Richard...
HPCA
2005
IEEE
14 years 5 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...