16 search results - page 2 / 4 » A Novel Low-Power Scan Design Technique Using Supply Gating |
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
VLSID
2006
IEEE
14 years 6 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...
SBCCI
2003
ACM
13 years 11 months ago
2003
ACM
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...