Sciweavers

Share
ASPDAC
2005
ACM

Sleep transistor sizing using timing criticality and temporal currents

10 years 6 months ago
Sleep transistor sizing using timing criticality and temporal currents
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to gate the power supply. This paper presents a new methodology based on timing criticality and temporal currents to size the sleep transistor. The timing criticality information and temporal current estimation are obtained using static timing analyzer. The results obtained indicate that our proposed technique results in area reduction of sleep transistors by 80% and 49% compared to module based design and cluster based design respectively.
Anand Ramalingam, Bin Zhang, Anirudh Devgan, David
Added 13 Oct 2010
Updated 13 Oct 2010
Type Conference
Year 2005
Where ASPDAC
Authors Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan
Comments (0)
books