590 search results - page 2 / 118 » A Novel Method to Improve the Test Efficiency of VLSI Tests |
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is b...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
ENGL
2007
13 years 4 months ago
2007
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper...