590 search results - page 3 / 118 » A Novel Method to Improve the Test Efficiency of VLSI Tests |
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
TCAD
2010
13 years 1 days ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
CEC
2010
IEEE
13 years 2 months ago
2010
IEEE
TestFul is a novel evolutionary testing approach for object-oriented programs with complex internal states. In our preliminary experiments, it already outperformed some of the well...