10 search results - page 2 / 2 » A Novel VLSI Architecture of Fixed-complexity Sphere Decoder |
ISVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
The authors present a turbo soft-in soft-out (SISO) decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
ISVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
ENGL
2008
13 years 5 months ago
2008
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
CASES
2009
ACM
13 years 9 months ago
2009
ACM
Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this...