24 search results - page 2 / 5 » A Power-Aware Prediction-Based Cache Coherence Protocol for ... |
TPDS
2008
13 years 4 months ago
2008
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
IEEEPACT
2005
IEEE
13 years 10 months ago
2005
IEEE
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous ...
ICPP
2009
IEEE
13 years 2 months ago
2009
IEEE
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
ASPLOS
2008
ACM
13 years 6 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...