27 search results - page 1 / 6 » A Robust Parallel Delta-Sigma A D Converter Architecture |
ISCAS
1995
IEEE
13 years 8 months ago
1995
IEEE
ISCAS
1995
IEEE
13 years 8 months ago
1995
IEEE
Abstract— This paper describes a new first and secondorder delta-sigma modulator (DSM) concept where the first integrator is extracted and implemented by a FM oscillator with t...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
There has been an increased interest in design of that it can give better performance, if a modified noise broadband (data rate >IMSPS) delta sigma ADCs with over- transfer func...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
A novel 0. 13,um CMOS integrated linear voltage to pulse delay time converter (VTC) is proposed. The VTC ml architecture uses current starved inverters where the inverter delay ver...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
In this work, we propose an enhanced design method for filterless class-D audio amplifier based on multilevel architecture. The multilevel technique consists of a multilevel conve...