Sciweavers

    23 search results - page 1 / 5
    » A Runtime Reconfigurable Implementation of the GSAT Algorith...
    Sort
    View
    FPL
    1999
    Springer
    115views Hardware» more  FPL 1999»
    A Runtime Reconfigurable Implementation of the GSAT Algorithm
    13 years 9 months ago
    A Runtime Reconfigurable Implementation of the GSAT Algorithm
    Download  www.cse.cuhk.edu.hk
    Wong Hiu Yung, Wing Seung Yuen, Kin-Hong Lee, Phil...
    claim paper
    Read More »
    JUCS
    2007
    102views more  JUCS 2007»
    The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
    13 years 4 months ago
    The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
    Download  www.jucs.org
    : This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
    Oscar Pérez, Yves Berviller, Camel Tanougas...
    claim paper
    Read More »
    IPPS
    2006
    IEEE
    144views Distributed And Parallel Com...» more  IPPS 2006»
    Implementation of a reconfigurable hard real-time control system for mechatronic and automotive applications
    13 years 11 months ago
    Implementation of a reconfigurable hard real-time control system for mechatronic and automotive applications
    Download  www.cecs.uci.edu
    Control algorithms implemented directly in hardware take advantage of parallel signal processing. Furthermore, implementing controller functionality in reconfigurable hardware fac...
    Steffen Toscher, Roland Kasper, Thomas Reinemann
    claim paper
    Read More »
    MAM
    2007
    157views more  MAM 2007»
    Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
    13 years 4 months ago
    Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
    Download  www.cse.secs.oakland.edu
    This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
    Darrin M. Hanna, Michael DuChene
    claim paper
    Read More »
    CODES
    2009
    IEEE
    173views Software Engineering» more  CODES 2009»
    Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
    13 years 8 months ago
    Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
    Download  infoscience.epfl.ch
    Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
    Vincenzo Rana, Srinivasan Murali, David Atienza, M...
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.