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ISCAS
1995
IEEE
95views Hardware» more  ISCAS 1995»
13 years 8 months ago
A Self-Test Approach Using Accumulators as Test Pattern Generators
: Configurations of adders and registers, which are available in tnany datapaths, can be utilized to generate pattems and to compact test responses. Thispaper unalyzes tlie patiern...
Albrecht P. Stroele
DELTA
2008
IEEE
13 years 11 months ago
AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis
Re-using embedded resources for implementing builtin self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement costefficient built-in self tes...
M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
ETS
2009
IEEE
79views Hardware» more  ETS 2009»
13 years 2 months ago
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
Michael A. Kochte, Christian G. Zoellin, Hans-Joac...
ICCAD
1994
IEEE
110views Hardware» more  ICCAD 1994»
13 years 9 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
VTS
1998
IEEE
97views Hardware» more  VTS 1998»
13 years 9 months ago
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...