Sciweavers

Share
ICCAD
1994
IEEE

Test pattern generation based on arithmetic operations

9 years 8 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation. In this paper, we propose a novel method for implementing test pattern generators based on adders widely available in data-path architectures and digital signal processing circuits. Test patterns are generated by continuously accumulating a constant value and their quality is evaluated in terms of the pseudo-exhaustive state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and area overhead.
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1994
Where ICCAD
Authors Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
Comments (0)
books