420 search results - page 1 / 84 » A Small Test Generator for Large Designs |
ITC
1992
IEEE
13 years 8 months ago
1992
IEEE
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
State space techniques have proven to be useful for measuring and improving the coverage of test vectors that are used during functional validation via simulation. By comparing th...
TCAD
2011
12 years 11 months ago
2011
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...