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ICASSP
2008
IEEE
14 years 2 days ago
High-performance scheduling algorithm for partially parallel LDPC decoder
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partia...
Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu
ICC
2007
IEEE
192views Communications» more  ICC 2007»
13 years 12 months ago
Informed Dynamic Scheduling for Belief-Propagation Decoding of LDPC Codes
— Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation, or message-passing, algorithm over the factor graph of the code. The tradi...
Andres I. Vila Casado, Miguel Griot, Richard D. We...
TCOM
2008
75views more  TCOM 2008»
13 years 5 months ago
Fast performance estimation of block codes
Importance sampling is used in this paper to address the classical yet important problem of performance estimation of block codes. Simulation distributions that comprise discretean...
Rajan Srinivasan, Nuo Wang
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
13 years 11 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
SIPS
2007
IEEE
13 years 12 months ago
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...