An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding

Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding of practical Low-Density Parity-Check (LDPC) codes on factor graphs. The proposed architecture makes fully-parallel decoding of (long) state-of-the-art LDPC codes viable on FPGAs. Implementation results for a (1024, 512) fully-parallel LDPC decoder shows an area requirement of about 36% of a Xilinx Virtex-4 XC4VLX200 device and a throughput of 706 Mbps at a bit-error-rate of about 10−6 with performance loss of about 0.1 dB, with respect to the nearly ideal floating-point sum-product algorithm with 32 iterations.

• Type: Conference
• Year: 2007
• Where: SIPS
• Authors: Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross
• Keywords: Fully-parallel Decoding, SIPS 2007, Stochastic Decoding, first Hardware Architecture