11 search results - page 2 / 3 » A Standard-Cell Placement Tool for Designs with High Row Uti... |
ISPD
2004
ACM
13 years 10 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
TCAD
2008
13 years 5 months ago
2008
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rate...
FPL
2007
Springer
13 years 11 months ago
2007
Springer
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPRO for placement and routing on ...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Many current integrated circuits designs, such as those released for the ISPD2005[14] placement contest, are extremely large and can contain a great deal of white space. These new...
SODA
2007
ACM
13 years 6 months ago
2007
ACM
Random geometric graphs have been one of the fundamental models for reasoning about wireless networks: one places n points at random in a region of the plane (typically a square o...