Performance-driven register insertion in placement

As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that require multiple clock cycles to propagate electrical signal are prevalent in many deep sub-micron designs. Efforts have been made to pipeline the long wires by introducing registers along these global paths, trying to reduce the impact of wire delay dominance [2, 8]. The technique of retiming to relocate registers in a circuit without affecting the circuit functionality can be applied in this problem. Though the problem of retiming with gate and wire delay has been studied recently [17, 1], the placement of registers after retiming is a new challenge. In this paper, we study the problem of realizing a retiming solution on a global netlist by inserting registers in the placement to achieve the target clock period. In contrast to many previous works [16, 11] that performed simple calculations to determine the po...

• Type: Conference
• Year: 2004
• Where: ISPD
• Authors: Dennis K. Y. Tong, Evangeline F. Y. Young
• Keywords: Clock Period, Hardware, ISPD 2004, Target Clock Period, Wire Delay