89 search results - page 3 / 18 » A Statistical Gate-Delay Model Considering Intra-Gate Variab... |
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
— As the technology scales into 90nm and below, process-induced variations become more pronounced. In this paper, we propose an efficient stochastic method for analyzing the vol...
DAC
2004
ACM
13 years 10 months ago
2004
ACM
Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inver...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...