Parametric yield estimation considering leakage variability

Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must consider the dependence of leakage current on frequency. In this paper, we present a new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability. We develop a closed-form equation for total chip leakage that models the dependence of the leakage current distribution on different process parameters. The proposed analytical expression is obtained directly from pertinent design information and includes both subthreshold and gate leakage currents. Using this model, we then present an integrated approach to accurately estimate the yield loss when both a frequency and power limits are imposed on a design. Our method demonstrates the importance of considering both these li...

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
• Keywords: Computer Architecture, DAC 2004, Leakage Current Exhibits, Leakage Currents, Total Leakage Current