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ISPD
2003
ACM
79views Hardware» more  ISPD 2003»
13 years 11 months ago
Floorplanning of pipelined array modules using sequence pairs
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
Matthew Moe, Herman Schmit
ICCAD
1993
IEEE
139views Hardware» more  ICCAD 1993»
13 years 10 months ago
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined a...
Ing-Jer Huang, Alvin M. Despain
DELTA
2006
IEEE
13 years 9 months ago
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
Jia Di, Dilip P. Vasudevan
ACSD
2005
IEEE
144views Hardware» more  ACSD 2005»
13 years 11 months ago
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
13 years 11 months ago
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma...