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» A System Level Resource Estimation Tool for FPGAs
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IPPS
2007
IEEE
13 years 11 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
ASAP
2009
IEEE
141views Hardware» more  ASAP 2009»
14 years 2 months ago
Accelerating a Virtual Ecology Model with FPGAs
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
Julien Lamoureux, Tony Field, Wayne Luk
ICSE
2003
IEEE-ACM
14 years 5 months ago
Architectural Level Risk Assessment Tool Based on UML Specifications
Recent evidences indicate that most faults in software systems are found in only a few of a system's components [1]. The early identification of these components allows an or...
T. Wang, Ahmed E. Hassan, Ajith Guedem, Walid Abde...
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
13 years 11 months ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
RSP
2006
IEEE
102views Control Systems» more  RSP 2006»
13 years 11 months ago
Rapid Resource-Constrained Hardware Performance Estimation
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrish...