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» A Taxonomy of Data Prefetching Mechanisms
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PLDI
1999
ACM
13 years 9 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
VISUALIZATION
1997
IEEE
13 years 9 months ago
GADGET: goal-oriented application design guidance for modular visualization environments
Modular Visualization Environments (MVEs) have recently been regarded as the de facto standard for scientific data visualization, mainly due to adoption of visual programming sty...
Issei Fujishiro, Yuriko Takeshima, Yoshihiko Ichik...
IPPS
2006
IEEE
13 years 11 months ago
Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems
High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
PUC
2008
113views more  PUC 2008»
13 years 4 months ago
Design and evaluation of systems to support interaction capture and retrieval
Although many recent systems have been built to support Information Capture and Retrieval (ICR), these have not generally been successful. This paper presents studies that evaluate...
Steve Whittaker, Simon Tucker, Kumutha Swampillai,...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 10 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...