89 search results - page 2 / 18 » A Technique for Speeding up the Solution of the Lagrangian D... |
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
—The Delay Filtered Dual Interlocked storage Cell (DF-DICE) offers a scalable solution in different radiation environments for soft error mitigation. The area and speed performan...
CORR
2007
Springer
13 years 5 months ago
2007
Springer
Abstract— We develop a general framework for MAP estimation in discrete and Gaussian graphical models using Lagrangian relaxation techniques. The key idea is to reformulate an in...
TCAD
2008
13 years 5 months ago
2008
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this paper we clarify a misunderstanding in using Lag...