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» A Technique to Reduce Peak Current and Average Power Dissipa...
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ASPDAC
2007
ACM
107views Hardware» more  ASPDAC 2007»
13 years 8 months ago
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
Seongmoon Wang, Wenlong Wei
VTS
2000
IEEE
126views Hardware» more  VTS 2000»
13 years 9 months ago
Static Compaction Techniques to Control Scan Vector Power Dissipation
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur ...
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
13 years 11 months ago
Reducing peak power with a table-driven adaptive processor core
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and de...
Vasileios Kontorinis, Amirali Shayan, Dean M. Tull...
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
14 years 1 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
ISCA
2003
IEEE
157views Hardware» more  ISCA 2003»
13 years 10 months ago
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
Michael D. Powell, T. N. Vijaykumar