10 search results - page 2 / 2 » A Timing-Constrained Algorithm for Simultaneous Global Routi... |
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
WADS
2001
Springer
13 years 9 months ago
2001
Springer
Abstract. We describe fully polynomial time approximation schemes for generalized multicommodity flow problems arising in VLSI applications such as Global Routing via Buffer Block...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which ma...
ISPD
1998
ACM
13 years 9 months ago
1998
ACM
—High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performan...