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ICCAD
2007
IEEE

Thermal-aware Steiner routing for 3D stacked ICs

9 years 3 months ago
Thermal-aware Steiner routing for 3D stacked ICs
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which makes it more general than its 2D counterpart. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show that thermal-aware 3D tree construction involves the minimization of two-variable Elmore delay function. In our tree refinement algorithm, we reposition the through-vias while preserving the original routing topology for further thermal optimization under performance constraint. We employ a novel scheme to relax the initial NLP formulation to ILP and consider all through-vias from all nets simultaneously. Our related experiments show the effectiveness of our proposed solutions.
Mohit Pathak, Sung Kyu Lim
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2007
Where ICCAD
Authors Mohit Pathak, Sung Kyu Lim
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