8 search results - page 2 / 2 » A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FP... |
DATE
2008
IEEE
14 years 7 days ago
2008
IEEE
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
GLVLSI
2006
IEEE
13 years 12 months ago
2006
IEEE
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...