7 search results - page 1 / 2 » A Two-State Methodology for RTL Logic Simulation |
DAC
1999
ACM
13 years 9 months ago
1999
ACM
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...
DATE
2010
IEEE
13 years 8 months ago
2010
IEEE
Due to increases in design complexity, routing a reset signal to all registers is becoming more difficult. One way to solve this problem is to reset only certain registers and rely...
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
DT
2000
13 years 4 months ago
2000
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...