This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Abstract. We present a novel counterexample generator for the interactive theorem prover Isabelle based on a compiler that synthesizes test data generators for functional programmi...
This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Inp...
This paper describes a unique approach to scheduling and allocation problem in high-level synthesis using genetic algorithm (GA). This approach is dierent from a previous attempt ...
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...