228 search results - page 2 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
FPL
2006
Springer
13 years 9 months ago
2006
Springer
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract—This paper presents a method to investigate powerperformance tradeoffs in digital pipelined designs. The method is applied at the architectural level of the design. It w...
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...