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    ISCAS
    2006
    IEEE
    109views Hardware» more  ISCAS 2006»
    A bit-serial approximate min-sum LDPC decoder and FPGA implementation
    13 years 11 months ago
    A bit-serial approximate min-sum LDPC decoder and FPGA implementation
    Download  www.eecg.toronto.edu
    Ahmad Darabiha, Anthony Chan Carusone, Frank R. Ks...
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    FCCM
    2003
    IEEE
    148views VLSI» more  FCCM 2003»
    A Hardware Gaussian Noise Generator for Channel Code Evaluation
    13 years 10 months ago
    A Hardware Gaussian Noise Generator for Channel Code Evaluation
    Download  www.ee.ucla.edu
    Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
    Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
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