183 search results - page 2 / 37 » A case for multi-level main memory |
ISCA
2007
IEEE
13 years 4 months ago
2007
IEEE
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
WMPI
2004
ACM
13 years 10 months ago
2004
ACM
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
BPSC
2009
13 years 5 months ago
2009
Abstract: In this paper we present our ideas to apply constraint satisfaction on business processes. We propose a multi-level constraint satisfaction approach to handle t levels of...
ICCD
1996
IEEE
13 years 9 months ago
1996
IEEE
The Multi-Level Decomposition Diagrams (MLDDs) of this paper are a canonical representation of Boolean functions expliciting disjoint-support decompositions. MLDDs allow the reduc...