121 search results - page 2 / 25 » A cell-based power estimation in CMOS combinational circuits |
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
MJ
2007
13 years 4 months ago
2007
Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the successful deployment of SAT technology in a wi...
ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
We present a transistor level power estimator which exploits algorithms for fast circuit simulation to compute the power dissipation of CMOS circuits. The proposed approach uses s...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...