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ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
9 years 5 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
CC
2001
Springer
176views System Software» more  CC 2001»
10 years 19 days ago
A Framework for Optimizing Java Using Attributes
Abstract. This paper presents a framework for supporting the optimization of Java programs using attributes in Java class files. We show how class file attributes may be used to ...
Patrice Pominville, Feng Qian, Raja Vallée-...
TCAD
2008
127views more  TCAD 2008»
9 years 8 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...
LCPC
2004
Springer
10 years 1 months ago
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism
Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor a...
Lakshmi N. Chakrapani, John C. Gyllenhaal, Wen-mei...
IJPP
2000
94views more  IJPP 2000»
9 years 8 months ago
Path Analysis and Renaming for Predicated Instruction Scheduling
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
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