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ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A dynamic test compaction procedure for high-quality path delay testing
- We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set...
Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, T...
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
13 years 9 months ago
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults
Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such ...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 1 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic