24 search results - page 3 / 5 » A dynamically reconfigurable cache for multithreaded process... |
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
CGO
2004
IEEE
13 years 9 months ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
SIGARCH
2008
13 years 5 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpM...
CASES
2010
ACM
13 years 3 months ago
2010
ACM
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...