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2010
ACM

Balancing memory and performance through selective flushing of software code caches

9 years 1 months ago
Balancing memory and performance through selective flushing of software code caches
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all platforms, and especially embedded systems. The memory demand is typically controlled by placing a limit on cached translations and forcing the DBT to flush all translations upon reaching the limit. This solution manifests as a performance inefficiency because many flushed translations require retranslation. Ideally, translations should be selectively flushed to minimize retranslations for a given memory limit. However, three obstacles exist: (1) it is difficult to predict which selections will minimize retranslation, (2) selective flushing results in greater book-keeping overheads than full flushing, and (3) the emergence of multicore processors and multi-threaded programming complicates most flushing algorithms. These issues have led to the widespread adoption of full flushing as a standard protocol. In thi...
Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
Added 10 Feb 2011
Updated 10 Feb 2011
Type Journal
Year 2010
Where CASES
Authors Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
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