6 search results - page 1 / 2 » A hierarchical decomposition methodology for multistage cloc... |
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order re...
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
- This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a un...
RSP
1998
IEEE
13 years 8 months ago
1998
IEEE
A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved co...