24 search results - page 3 / 5 » A loop accelerator for low power embedded VLIW processors |
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
EMSOFT
2004
Springer
13 years 10 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
Entropy encoding and decoding is a crucial part of any multimedia system that can be highly demanding in terms of computing power. Hardware implementation of typical compression a...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- TOSHIBA has developed mobile multi-media engine SoC, we call as S1G, which can realize low power ISDB-T one-segment decode in 42mW for eight months short period of time. Since MP...
CODES
2008
IEEE
13 years 11 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...